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rev. b information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a serial-port 16-bit soundport stereo codec AD1847 ? analog devices, inc., 1996 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 617/329-4700 fax: 617/326-8703 features single-chip integrated sd digital audio stereo codec supports the microsoft windows sound system* multiple channels of stereo input analog and digital signal mixing programmable gain and attenuation on-chip signal filters digital interpolation and decimation analog output low-pass sample rates from 5.5 khz to 48 khz 44-lead plcc and tqfp packages operation from +5 v supplies serial digital interface compatible with adsp-21xx fixed-point dsp i s a b u s asic AD1847 dsp figure 1. example system diagram external circuit requirements are limited to a minimal number of low cost support components. anti-imaging dac output filters are incorporated on-chip. dynamic range exceeds 70 db over the 20 khz audio band. sample rates from 5.5 khz to 48 khz are supported from external crystals. the codec includes a stereo pair of ?d analog-to-digital con- verters (adcs) and a stereo pair of ?d digital-to-analog con- verters (dacs). inputs to the adc can be selected from four stereo pairs of analog signals: line 1, line 2, auxiliary (aux) line #1, and post-mixed dac output. a software-controlled programmable gain stage allows independent gain for each channel going into the adc. the adcs output can be digitally mixed with the dacs input. the pair of 16-bit outputs from the adcs is available over a se- rial interface that also supports 16-bit digital input to the dacs and control/status information. the AD1847 can accept and generate 16-bit twos-complement pcm linear digital data, 8-bit unsigned magnitude pcm linear data, and 8-bit m -law or a-law companded digital data. (continued on page 7) functional block diagram analog i/o l r digital i/o crystals 2 2 2 s e r i a l p o r t oscillators 2.25v reference l r l r clock out atten digital supply analog supply m u x l r l r l r l r bus master time slot input time slot output serial data output serial data input external control serial bit clock frame sync reset line 1 input line 2 input aux 1 input line output aux 2 input AD1847 ? atten/ mute atten power down m /a law m /a law atten ? ? ? ?d d/a converter ?d d/a converter m /a law m /a law gain gain ?d a/d converter ?d a/d converter gain/atten/mute gain/atten /mute gain/atten /mute atten/ mute product overview the AD1847 soundport ? stereo codec integrates key audio data conversion and control functions into a single integrated circuit. the AD1847 is intended to provide a complete, low cost, single-chip solution for business, game audio and multi- media applications requiring operation from a single +5 v sup- ply. it provides a serial interface for implementation on a computer motherboard, add-in or pcmcia card. see figure 1 for an example system diagram. *windows sound system is a registered trademark of microsoft corp. soundport is a registered trademark of analog devices, inc.
standard test conditions unless otherwise noted temperature 25 c dac output conditions digital supply (v dd ) 5.0 v 0 db attenuation analog supply (v cc ) 5.0 v full-scale digital inputs word rate (f s ) 48 khz 16-bit linear mode input signal 1007 hz no output load analog output passband 20 hz to 20 khz mute off fft size 4096 adc input conditions v ih 2.4 v 0 db gain v il 0.8 v C3.0 db relative to full scale v oh 2.4 v line input v ol 0.4 v 16-bit linear mode analog input min typ max units full-scale input voltage (rms values assume sine wave input) line1, line2, aux1, aux2 1 v rms 2.54 2.8 3.10 v p-p input impedance line1, line2, aux1, aux2? 10 k w input capacitance? 15 pf programmable gain amplifieradc min typ max units step size (all steps tested, C30 db input) 1.10 1.5 1.90 db pga gain range span? 21.0 24.0 db auxiliary input analog amplifiers/attenuators min typ max units step size (+12 db to C28.5 db, referenced to dac full scale) 1.3 1.5 1.7 db (C30 db to C34.5 db, referenced to dac full scale) 1.1 1.5 1.9 db input gain/attenuation range span? 45.5 47.5 db aux input impedance? 10 k w digital decimation and interpolation filters? min max units passband 0 0.4 3 f s hz passband ripple C0.1 +0.1 db transition band 0.4 3 f s 0.6 3 f s hz stopband 0.6 3 f s hz stopband rejection 74 db group delay 30/f s group delay variation over passband 0 m s rev. b AD1847Cspecifications C2C
analog-to-digital converters min typ max units resolution 16 bits dynamic range (C60 db input, thd+n referenced to full scale, a-weighted) 70 db thd+n (referenced to full scale) 0.040 % C68 db signal-to-intermodulation distortion? 83 db adc crosstalk? line inputs (input l, ground r, read r; input r, ground l, read l) C80 db line1 to line2 (input line1, ground and select line2, read both channels) C80 db line to aux1 C80 db line to aux2 C80 db line to dac C80 db gain error (full-scale span relative to v refi ) 10 % interchannel gain mismatch (difference of gain errors) 0.2 db dc offset 55 lsb digital-to-analog converters min typ max units resolution 16 bits dynamic range (C60 db input, thd+n referenced to full scale, a-weighted) 76 db thd+n (referenced to full scale) 0.025 % C72 db signal-to-intermodulation distortion? 86 db gain error (full-scale span relative to v refi ) 10 % interchannel gain mismatch (difference of gain errors) 0.2 db dac crosstalk? (input l, zero r, measure r_out; input r, zero l, measure l_out) C80 db total out-of-band energy? (measured from 0.6 3 f s to 100 khz) C50 db audible out-of-band energy (measured from 0.6 3 f s to 22 khz, tested at f s = 5.5 khz) C55 db dac attenuator min typ max units step size (0 db to C22.5 db) (tested at steps 0 db, C19.5) 1.3 1.5 1.7 db step size (C24 db to C94 db) 1.0 1.5 2.0 db output attenuation range span? C93 95 db digital mix attenuator min typ max units step size (0 db to C22.5 db) (tested at steps 0 db, C19.5) 1.3 1.5 1.7 db step size (C24 db to C94 db) 1.0 1.5 2.0 db output attenuation range span? C93.5 95.5 db analog output min typ max units full-scale line output voltage 0.707 v rms v refi = 2.35* 1.80 2 2.20 v p-p line output impedance? 600 w external load impedance 10 k w output capacitance? 15 pf external load capacitance 100 pf v ref (clock running) 2.00 2.50 v v ref current drive 100 m a v refi 2.35 v mute attenuation of 0 db C80 db fundamental? (lout) mute click? 8mv (|muted output minus unmuted midscale dac output|) *full-scale line output voltage scales with v ref (e.g., v out (typ) C 2.0 v 3 (v ref /2.35)). ?guaranteed, not tested. rev. b C3C AD1847
AD1847 rev. b C4C system specifications min typ max units system frequency response? 0.3 db (line in to line out, 20 hz to 20 khz) differential nonlinearity? 1/2 bit phase linearity deviation? 1 degrees static digital specifications min max units high level input voltage (v ih ) digital inputs 2.0 v xtal1/2i 2.4 v low level input voltage (v il ) 0.8 v high level output voltage (v oh ) i oh = 1 ma 2.4 v dd v low level output voltage (v ol ) i ol = 4 ma 0.4 v input leakage current (go/nogo tested) C10 +10 m a output leakage current (go/nogo tested) C10 +10 m a timing parameters (guaranteed over operating temperature range) min typ max units serial frame sync period (t 1 ) 1/0.5 f s m s clock to frame sync [sdfs] propagation delay (t pd1 )20ns data input setup time (t s )15 ns data input hold time (t h )15 ns clock to output data valid (t dv ) 25 ns clock to output three-state [high-z] (t hz )20ns clock to time slot output [tso] propagation delay (t pd2 )20ns reset and pwrdown lo pulse width (t rpwl ) 100 ns power supply min max units power supply range C digital & analog 4.75 5.25 v power supply current C operating (10 k w line out load) 140 ma analog supply current C operating (10 k w line out load) 70 ma digital supply current C operating (10 k w line out load) 70 ma analog power supply current C power down 400 m a digital power supply current C power down 400 m a power dissipation C operating (current 3 nominal supply) 750 mw power dissipation C power down (current 3 nominal supply) 4 mw power supply rejection (@ 1 khz)? (at both analog and digital supply pins, adcs) 45 db (at both analog and digital supply pins, dacs) 55 db clock specifications? min max units input clock frequency 27 mhz recommended clock duty cycle 10 % initialization/sample rate change time 16.9344 mhz crystal selected at power-up 171 ms 24.576 mhz crystal selected at power-up 171 ms 16.9344 mhz crystal selected subsequently 6 ms 24.576 mhz crystal selected subsequently 6 ms ?guaranteed, not tested. specifications subject to change without notice.
AD1847 rev. b C5C absolute maximum ratings* min max units power supplies digital (v dd ) C0.3 6.0 v analog (v cc ) C0.3 6.0 v input current (except supply pins) 10.0 ma analog input voltage (signal pins) C0.3 (va+) + 0.3 v digital input voltage (signal pins) C0.3 (vd+) + 0.3 v ambient temperature (operating) 0 +70 c storage temperature C65 +150 c *stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. ordering guide temperature package package model range description option* AD1847jp 0 c to +70 c 44-lead plcc p-44a AD1847jst 0 c to +70 c 44-lead tqfp st-44 *p = plcc; st = tqfp. warning! esd sensitive device caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the AD1847 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. 44-lead plcc 44-lead tqfp r_line2 rfilt l_line2 l_line1 gnda gnda lfilt l_aux1 r_aux1 r_out v cc sdfs sdo v dd sclk clkout sdi gndd xtal2i xtal1o xtal1i xtal2o v dd gndd gndd v dd bm xctl1 xctl0 r_aux2 l_out n/c l_aux2 44 1 2 64 5 21 24 23 22 18 20 19 39 38 35 34 33 37 36 3 7 8 11 12 13 9 10 40 41 42 25 28 27 26 43 31 30 29 32 15 16 17 14 top view (not to scale) AD1847jp tso tsi reset pwrdown v cc v dd gndd v refi v ref r_line1 gnda n/c = no connect 44 sdfs 43 sdo 42 sdi 41 gndd 40 v dd 39 sclk 38 clkout 37 xtal2o 36 xtal2i 35 xtal1o 34 xtal1i 33 32 31 30 29 28 27 26 25 24 23 pin 1 identifier r_line1 v ref v refi gnda v cc pwrdown reset gndd v dd tsi tso 1 2 3 4 5 6 7 8 9 11 10 v dd gndd xctl1 xctl0 gndd v dd bm l_aux2 r_aux2 l_out n/c r_line2 12 rfilt 13 gnda 14 lfilt 15 l_line2 16 l_line1 17 gnda 18 l_aux1 20 r_aux1 21 r_out 22 v cc 19 top view (not to scale) AD1847jst n/c = no connect pinouts
AD1847 rev. b C6C pin descriptions parallel interface pin name plcc tqfp i/o description sclk 1 39 i/o serial clock. sclk is a bidirectional signal that supplies the clock as an output to the serial bus when the bus master (bm) pin is driven hi and accepts the clock as an input when the bm pin is driven lo. the serial clock output is fixed at 12.288 mhz when xtal1 is selected, and 11.2896 mhz when xtal2 is selected. sclk runs continu- ously. an AD1847 should always be configured as the serial bus master unless it is a slave in a daisy-chained multiple codec system. sdfs 6 44 i/o serial data frame sync. sdfs is a bidirectional signal that supplies the frame synchroni- zation signal as an output to the serial bus when the bus master (bm) pin is driven hi and accepts the frame synchronization signal as an input when the bm pin is driven lo. the sdfs frequency powers up at one half of the AD1847 sample rate (i.e., frs bit = 0) with two samples per frame and can be programmed to match the sample rate (i.e., frs bit = 1) with one sample per frame. an AD1847 should always be configured as the serial bus master unless it is a slave in a daisy-chained multiple codec system. sdi 4 42 i serial data input. sdi is used by peripheral devices such as the host cpu or a dsp to supply control and playback data information to the AD1847. all control and playback transfers are 16 bits long, msb first. sdo 5 43 o serial data output. sdo is used to supply status/index readback and capture data infor- mation to peripheral devices such as the host cpu or a dsp. all status/index readback and capture data transfers are 16 bits long, msb first. three-state output driver. reset 11 5 i reset. the reset signal is active lo. the assertion of this signal will initialize the on-chip registers to their default values. see the control register definitions section for a description of the contents of the control registers after reset is deasserted. pwrdown 12 6 i powerdown. the pwrdown signal is active lo. the assertion of this signal will reset the on-chip control registers (identically to the reset signal) and will also place the AD1847 in a low power consumption mode. v ref and all analog circuitry are disabled. bm 33 27 i bus master. the assertion (hi) of this signal indicates that the AD1847 is the serial bus master. the AD1847 will then supply the serial clock (sclk) and the frame sync (sdfs) signals for the serial bus. one and only one AD1847 should always be configured as the serial bus master. if bm is connected to logic lo, the AD1847 is configured as a bus slave, and will accept the sclk and sdfs signals as inputs. an AD1847 should only be configured as a serial bus slave when an AD1847 serial bus master already exists, in daisy-chained multiple codec systems. tso 7 1 o time slot output. this signal is asserted hi by the AD1847 coincidentally with the lsb of the last time slot used by the AD1847. used in daisy-chained multiple codec systems. tsi 8 2 i time slot input. the assertion of this signal indicates that the AD1847 should immedi- ately use the next three time slots (tssel = 1) or the next six time slots (tssel = 0) and then activate the tso pin to enable the next device down the tdm chain. tsi should be driven lo when the AD1847 is the bus master or in single codec systems. used in daisy-chained multiple codec systems. clkout 44 38 o clock output. this signal is the buffered version of the crystal clock output and the fre- quency is dependent on which crystal is selected. this pin can be three-stated by driving the bm pin lo or by programming the clkts bit in the pin control register. see the control registers section for more details. the clkout frequency is 12.288 mhz when xtal1 is selected and 16.9344 mhz when xtal2 is selected. analog signals pin name plcc tqfp i/o description l_line1 23 17 i left line input #1. line level input for the #1 left channel. r_line1 17 11 i right line input #1. line level input for the #1 right channel. l_line2 22 16 i left line input #2. line level input for the #2 left channel. r_line2 18 12 i right line input #2. line level input for the #2 right channel. l_aux1 26 20 i left auxiliary input #1. line level input for the aux1 left channel. r_aux1 27 21 i right auxiliary input #1. line level input for the aux1 right channel. l_aux2 32 26 i left auxiliary input #2. line level input for the aux2 left channel. r_aux2 31 25 i right auxiliary input #2. line level input for the aux2 right channel. l_out 30 24 o left line output. line level output for the left channel. r_out 28 22 o right line output. line level output for the right channel.
AD1847 rev. b C7C miscellaneous pin name plcc tqfp i/o description xtal1i 40 34 i 24.576 mhz crystal #1 input. xtal1o 41 35 o 24.576 mhz crystal #1 output. xtal2i 42 36 i 16.9344 mhz crystal #2 input. xtal2o 43 37 o 16.9344 mhz crystal #2 output. xctl1:o 37 & 36 31 & 30 o external control. these ttl signals reflect the current status of register bits inside the AD1847. they can be used for signaling or to control external logic. v ref 16 10 o voltage reference. nominal 2.25 volt reference available externally as a voltage datum for dc-coupling and level-shifting. v ref should not have any signal dependent load. v refi 15 9 i voltage reference internal. voltage reference filter point for external bypassing only. l_filt 21 15 i left channel filter capacitor. this pin requires a 1.0 m f capacitor to analog ground for proper operation. r_filt 19 13 i right channel filter capacitor. this pin requires a 1.0 m f capacitor to analog ground for proper operation. nc 29 23 no connect. do not connect. power supplies pin name plcc tqfp i/o description v cc 13 & 25 7 & 19 i analog supply voltage (+5 v). gnda 14, 20, 24 8, 14, 18 i analog ground. v dd 2, 9, 34, 39 40, 3, 28, 33 i digital supply voltage (+5 v). gndd 3, 10, 35, 38 41, 4, 29, 32 i digital ground. (continued from page 1) the ?d dacs are preceded by a digital interpolation filter. an attenuator provides independent user volume control over each dac channel. nyquist images are removed from the dacs analog stereo output by on-chip switched-capacitor and continuous-time filters. two stereo pairs of auxiliary line-level inputs can also be mixed in the analog domain with the dac output. the AD1847 serial data interface uses a time division multi- plex (tdm) scheme that is compatible with dsp serial ports configured in multi-channel mode with 32 16-bit time slots (i.e., sport0 on the adsp-2101, adsp-2115, etc.). audio functional description this section overviews the functionality of the AD1847 and is intended as a general introduction to the capabilities of the de- vice. as much as possible, detailed reference information has been placed in control registers and other sections. the user is not expected to refer repeatedly to this section. analog inputs the AD1847 soundport stereo codec accepts stereo line-level inputs. all inputs should be capacitively coupled (ac-coupled) to the AD1847. line1, line2, and aux1, and post-mixed dac output analog stereo signals are multiplexed to the internal pro- grammable gain amplifier (pga) stage. the pga following the input multiplexer allows independent selectable gains for each channel from 0 to 22.5 db in +1.5 db steps. the codec can operate either in a global stereo mode or in a global mono mode with left-channel inputs appearing at both channel outputs. analog mixing aux1 and aux2 analog stereo signals can be mixed in the ana- log domain with the dac output. each channel of each auxil- iary analog input can be independently gained/attenuated from +12 db to C34.5 db in C1.5 db steps or completely muted. the post-mixed dac output is available on l_out and r_out externally and as an input to the adcs. even if the AD1847 is not playing back data from its dacs, the analog mix function can still be active. analog-to-digital datapath the ?d adcs incorporate a proprietary fourth-order modula- tor. a single pole of passive filtering is all that is required for antialiasing the analog input because of the adcs high 64 times oversampling ratio. the adcs include digital decimation filters that low-pass filter the input to 0.4 3 f s . (f s is the word rate or sampling frequency.) adc input overrange con- ditions will cause status bits to be set that can be read. digital-to-analog datapath the ?d dacs contain a programmable attenuator and a low- pass digital interpolation filter. the anti-imaging interpolation filter oversamples and digitally filters the higher frequency im- ages. the attenuator allows independent control of each dac channel from 0 db to C94.5 db in 1.5 db steps plus full mute. the dacs ?d noise shapers also oversample and convert the signal to a single-bit stream. the dac outputs are then filtered in the analog domain by a combination of switched-capacitor and continuous-time filters. these filters remove the very high frequency components of the dac bitstream output. no exter- nal components are required.
AD1847 rev. b C8C changes in dac output attenuation take effect only on zero crossings of the digital signal, thereby eliminating zipper noise on playback. each channel has its own independent zero-cr ossing detector and attenuator change control circuitry. a timer guar- antees that requested volume changes will occur even in the ab- sence of an input signal that changes sign. the time-out period is 8 milliseconds at a 48 khz sampling rate and 48 milliseconds at an 8 khz sampling rate. (time-out [ms] ? 384/f s [khz]). digital mixing stereo digital output from the adcs can be mixed digitally with the input to the dacs. digital output from the adcs going out of the serial data port is unaffected by the digital mix. along the digital mix datapath, the 16-bit linear output from the adcs is attenuated by an amount specified with control bits. both chan- nels of the monitor data are attenuated by the same amount. (note that internally the AD1847 always works with 16-bit pcm linear data, digital mixing included; format conversions take place at the input and output.) sixty-four steps of C1.5 db attenuation are supported to C94.5 db. the digital mix datapath can also be completely muted, preventing any mixing of the digital input with the digi- tal output. note that the level of the mixed signal is also a func- tion of the input pga settings, since they affect the adcs output. the attenuated digital mix data is digitally summed with the dac input data prior to the dacs datapath attenuators. the digital sum of digital mix data and dac input data is clipped at plus or minus full scale and does not wrap around. because both stereo signals are mixed before the output attenuators, mix data is attenuated a second time by the dacs datapath attenuators. analog outputs a stereo line-level output is available at external pins. other output types such as headphone and speaker must be imple- mented in external circuitry. the stereo line-level outputs should be capacitively coupled (ac-coupled) to the external cir- cuitry. each channel of this output can be independently muted. when muted, the outputs will settle to a dc value near v ref , the midscale reference voltage. digital data types the AD1847 supports four global data types: 16-bit twos- complement linear pcm, 8-bit unsigned linear pcm, companded m -law, and 8-bit companded a-law, as specified by control register bits. eight-bit data is always left-justified in 16- bit fields; in other words, the msbs of all data types are always aligned; in yet other words, full-scale representations in all four form ats corre spond to equivalent full-scale signals. the eight least significant bit positions of 8-bit data in 16-bit fields are ig- nored on digital input and zoned on digital output (i.e., truncated). the 16-bit pcm data format is capable of representing 96 db of dynamic range. eight-bit pcm can represent 48 db of dynamic range. companded m -law and a-law data formats use nonlinear coding with less precision for large-amplitude signals. the loss of precision is compensated for by an increase in dynamic range to 64 db and 72 db, respectively. on input, 8-bit companded data is expanded to an internal lin- ear representation, according to whether m -law or a-law was specified in the codecs internal registers. note that when m -law compressed data is expanded to a linear format, it requires 14 bits. a-law data expanded requires 13 bits. expansion dac input msb lsb 15 0 msb 15 0 msb 15 0 compressed input data lsb 3/2 2/1 lsb 3/2 2/1 0 0 0 / 0 0 87 figure 2. a-law or m -law expansion when 8-bit companding is specified, the adcs linear output is compressed to the format specified. truncation compression msb lsb 15 0 msb lsb 15 0 msb lsb 15 0 3/2 2/1 adc output 0 0 0 0 0 0 0 0 87 figure 3. a-law or m -law compression note that all format conversions take place at input or output. internally, the AD1847 always uses 16-bit linear pcm represen- tations to maintain maximum precision. power supplies and voltage reference the AD1847 operates from +5 v power supplies. independent analog and digital supplies are recommended for optimal perfor- mance though excellent results can be obtained in single-supply systems. a voltage reference is included on the codec and its 2.25 v buffered output is available on an external pin (v ref ). the reference output can be used for biasing op amps used in dc coupling. the internal reference must be externally bypassed to analog ground at the v refi pin, and must not be used to bias external circuitry. clocks and sample rates the AD1847 operates from two external crystals, xtal1 and xtal2. the two crystal inputs are provided to generate a wide range of sample rates. the oscillators for these crystals are on the AD1847, as is a multiplexer for selecting between them. they can be overdriven with external clocks by the user, if so desired. at a minimum, xtal1 must be provided since it is se- lected as the reset default. if xtal2 is not used, the xtal2 input pin should be connected to ground. the recommended crystal frequencies are 16.9344 mhz and 24.576 mhz. from them, the following sample rates can be selected: 5.5125, 6.615, 8, 9.6, 11.025, 16, 18.9, 22.05, 27.42857, 32, 33.075, 37.8, 44.1, 48 khz.
AD1847 rev. b C9C control registers control register mapping the AD1847 has six 16-bit and thirteen 8-bit on-chip user- accessible control registers. control information is sent to the AD1847 in the 16-bit control word. status information is sent from the AD1847 in the 16-bit status word. playback data and capture data each have two 16-bit registers for the right and left channels. additional 8-bit index registers are accessed via indirect addressing in the AD1847 control word. [index regis- ters are reached with indirect addressing.] the contents of an indirect addressed index register may be readback by the host cpu or dsp (during the status word/index readback time slot) by setting the read request (rreq) bit in the control word. note that each 16-bit register is assigned its own time slot, so that the AD1847 always consumes six 16-bit time slots. figure 4 shows the mapping of the control word, status word/ index readback and data registers to time slots when tssel = 0. tssel = 0 is used when the sdi and sdo pins are tied to- gether (i.e., 1-wire system). this configuration is efficient in terms of component interconnect (one bidirectional wire for se- rial data input and output), but inefficient in terms of time slot usage (six slots consumed on single bidirectional time division multiplexed [tdm] serial bus). when tssel = 0, serial data input to the AD1847 occurs sequentially with serial data output from the AD1847 (i.e., control word, left playback and right playback data is received on the sdi pin, then the status word/ lndex readback, left capture and right capture data is trans- mitted on the sdo pin). slot register name (16-bit) 0 control word input 1 left playback data input 2 right playback data input 3 status word/index readback output 4 left capture data output 5 right capture data output figure 4. control register mapping with tssel = 0 figure 5 shows the mapping of the control word, status word/ index readback and data registers to time slots when tssel = 1. note that the six 16-bit registers share three time slots. tssel = 1 is used when the sdi and sdo pins are indepen- dent inputs and output (i.e., 2-wire system). this configura- tion is inefficient in terms of component interconnect (two unidirectional wires for serial data input and output), but effi- cient in terms of time slot usage (three slots consumed on each of two unidirectional tdm serial buses). when tssel = 1, se- rial data input to the AD1847 occurs concurrently with serial data output from the AD1847 (i.e., control word reception on the sdi pin occurs simultaneously with status word/lndex readback transmission on the sdo pin). slot register name (16-bit) 0 control word input 1 left playback data input 2 right playback data input 0 status word/index readback output 1 left capture data output 2 right capture data output figure 5. control register mapping with tssel = 1 an index register readback request to an invalid index address (11, 14 and 15) will return the contents of the status word. at- tempts to write to an invalid index address (11, 14 and 15) will have no effect on the AD1847. as mentioned above, the rreq bit of the control word is used to request status word output or index register readback output during either time slot 3 (tssel = 0) or time slot 0 (tssel = 1). rreq is set for in- dex register readback output, and reset for status word output. when index register readback is requested, the index readback bit format is the same as the control word bit format. all status bits are updated by the AD1847 before a new control word is received (i.e., at frame boundaries). thus, if tssel = 0 and the control word written at slot 0 causes some status bits to change, the change will show up in the status word transmitted at slot 3 of the same sample.
AD1847 rev. b C10C control word (16-bit) data 15 data 14 data 13 data 12 data 11 data 10 data 9 data 8 clor mce rreq res ia3 ia2 ia1 ia0 data 7 data 6 data 5 data 4 data 3 data 2 data 1 data 0 data7 data6 data5 data4 data3 data2 data1 data0 data7:0 index register data. these bits are the data for the desired AD1847 index register referenced by the index address. written by the host cpu or dsp to the AD1847. ia3:0 index register address. these bits define the indirect address of the desired AD1847 index register. written by the host cpu or dsp to the AD1847. rreq read request. setting this bit indicates that the current transfer is a request by the host cpu or dsp for readback of the contents of the indirect addressed index register. when this bit is set (rreq = hi), the AD1847 will not transmit its status word in the following status word index readback slot, but will instead transmit the data in the index register specified by the index address. although the index readback is transmitted in the following status word/index readback time slot, the format of the control word is used (i.e., clor, mce, rreq and the index register address in the most significant byte, and the readback index register data in the least significant byte). when this bit is reset (rreq = lo), the AD1847 will transmit its status word in the following status word index readback time slot. a read request is serviced in the next available index readback time slot. if tssel = 0, the index register readback data is transmitted in slot 3 of the same sample. if tssel = 1, index register readback data is transmitted in slot 0 of the next sample. if tssel changes from 0 to 1, index register readback will occur twice, in slot 3 of the current sample, and slot 0 of the next. if tssel changes from 1 to 0, the last read request is lost. res reserved for future expansion. write zeros (lo) to all reserved bits. mce mode change enable. this bit must be set (mce = hi) whenever protected control register bits of the AD1847 are changed. the data format register, the miscellaneous information register, and the acal bit of the interface configu- ration register can not be changed unless this bit is set. the dac outputs will be muted when mce is set. the user must mute the aux1 and aux2 channels when this bit is set (no audio activity should occur). written by the host cpu or dsp to the AD1847. this bit is hi after reset. clor clear overrange. when this bit is set (clor = hi), the overrange bits in the status word are updated every sample. when this bit is reset (clor = lo), the overrange bits in the status word will record the largest overrange value. the largest overrange value is sticky until the clor bit is set. written by the host cpu or dsp to the AD1847. since there can be up to 2 samples in the data pipeline, a change to clor may take up to 2 samples periods to take effect. this bit is hi after reset. immediately after reset, the contents of this register is: 1100 0000 0000 0000 (c000h). left/right playback/capture data (16-bit) the data formats for left playback, right playback, left capture and right capture are all identical. data 15 data 14 data 13 data 12 data 11 data 10 data 9 data 8 data15 data14 data13 data12 data11 data10 data9 data8 data 7 data 6 data 5 data 4 data 3 data 2 data 1 data 0 data7 data6 data5 data4 data3 data2 data1 data0 data15:0 data bits. these registers contain the 16-bit, msb first data for capture and playback. the host cpu or dsp reads the capture data from the AD1847. the host cpu or dsp writes the playback data to the AD1847. for 8-bit linear or 8-bit companded modes, only data15:8 contain valid data; data7:0 are ignored during capture, and are zeroed during playback. mono mode plays back the same audio sample on both left and right channels. mono capture only captures data from the left audio channel. see serial data format timing diagram. immediately after reset, the content of these registers is: 0000 0000 0000 0000 (0000h).
AD1847 rev. b C11C status word (16-bit) data 15 data 14 data 13 data 12 data 11 data 10 data 9 data 8 res res rreq res id3 id2 id1 id0 data 7 data 6 data 5 data 4 data 3 data 2 data 1 data 0 res res orr1 orr0 orl1 orl0 aci init init initialization. this bit is an indication to the host that frame syncs will stop and the serial bus will be shut down. init is set hi on the last valid frame. it is reset lo for all other frames. read by the host cpu or dsp from the AD1847. the init bit is set hi on the last sample before the serial interface is inactivated. the only condition under which the init bit is set is when a different sample rate is programmed. if frs = 0 (32 slots per frame, two samples per frame) and the sample rate is changed in the first sample of the 32 slot frame (i.e., during slots 0 through 15), the init bit will be set on the second sample of that frame (i.e., during slots 16 through 31). if frs = 0 and the sample rate is changed in the second sample of the 32 slot frame, the init bit will be set on the second sample of the following frame. aci autocalibrate in-progress. this bit indicates that autocalibration is in progress or the mode change enable (mce) state has been recently exited. when exiting the mce state with the acal bit set, the aci bit will be set hi for 384 sample periods. when exiting the mce state with the acal bit reset, the acal bit will be set hi for 128 sample periods, indi- cating that offset and filter values are being restored. read by the host cpu or dsp from the AD1847. 0 autocalibration not in progress 1 autocalibration is in progress aci clear (i.e., reset or lo) should be recognized by first polling for a hi on the sample after the mce bit is reset, and then polling for a lo. note that it is important not to start polling until one sample after mce is reset, because if mce is set while aci is hi, an aci lo on the following sample will suggest a false clear of aci. orl1:0 overrange left detect. these bits indicate the overrange on the left input channel. read by the host cpu or dsp from the AD1847. 0 greater than C1.0 db underrange 1 between C1.0 db and 0 db underrange 2 between 0 db and 1.0 db overrange 3 greater than 1.0 db overrange orr1:0 overrange right detect. these bits indicate the overrange on the right input channel. read by the host cpu or dsp from the AD1847. 0 greater than C1.0 db underrange 1 between C1.0 db and 0 db underrange 2 between 0 db and 1.0 db overrange 3 greater than 1.0 db overrange id3:0 AD1847 revision id. these four bits define the revision level of the AD1847. the first version of the AD1847 is desig- nated id = 0001. read by the host cpu or dsp from the AD1847. rreq this bit is reset lo for the status word, echoing the rreq state written by the host cpu or dsp in the previous con- trol word. read by the host cpu or dsp from the AD1847. res reserved for future expansion. all reserved bits read zero (lo). immediately after reset, the contents of this register is: 0000 0001 0000 0000 (0100h).
AD1847 rev. b C12C index readback (16-bit) data 15 data 14 data 13 data 12 data 11 data 10 data 9 data 8 clor mce rreq res ia3 ia2 ia1 ia0 data 7 data 6 data 5 data 4 data 3 data 2 data 1 data 0 data7 data6 data5 data4 data3 data2 data1 data0 data7:0 index register data. these bits are the readback data from the desired AD1847 index register referenced by the index address from the previous control word (with the rreq bit set). read by the host cpu or dsp from the AD1847. ia3:0 index register address. these bits echo the indirect address (written during the previous control word (with the rreq bit set) of the desired AD1847 index register to be readback. read by the host cpu or dsp from the AD1847. rreq read request. this bit is set hi for index readback, echoing the rreq state written by the host cpu or dsp in the previous control word. read by the host cpu or dsp from the AD1847. res reserved for future expansion. all reserved bits read zero (lo). mce mode change enable. this bit echoes the mce state written by the host cpu or dsp during the previous* control word (with the rreq bit set). read by the host cpu or dsp from the AD1847. clor clear overrange. this bit echoes the clor state written by the host cpu or dsp during the previous control word (with the rreq bit set). read by the host cpu or dsp from the AD1847. immediately after reset, the contents of this register is: 1110 0000 0000 0000 (e000h). indirect mapped registers following in figure 6 is a table defining the mapping of AD1847 8-bit index registers to index address. these registers are accessed by writing the appropriate 4-bit index address in the control word. index register name 0 left input control 1 right input control 2 left aux #1 input control 3 right aux #l input control 4 left aux #2 input control 5 right aux #2 input control 6 left dac control 7 right dac control 8 data format 9 interface configuration 10 pin control 11 invalid address 12 miscellaneous information 13 digital mix control 14 invalid address 15 invalid address figure 6. index register mapping a detailed description of each of the index registers is given below.
AD1847 rev. b C13C left input control register (index address 0) ia3:0 data 7 data 6 data 5 data 4 data 3 data 2 data 1 data 0 0000 lss1 lss0 res res lig3 lig2 lig1 lig0 lig3:0 left input gain select. the least significant bit of this 16-level gain select represents +1.5 db. maximum gain is +22.5 db. res reserved for future expansion. write zeros (lo) to all reserved bits. lss1:0 left input source select. these bits select the input source for the left gain stage preceding the left adc. 0 left line 1 source selected 1 left auxiliary 1 source selected 2 left line 2 source selected 3 left line 1 post-mixed output loopback source selected this registers initial state after reset is: 0000 0000 (00h). right input control register (index address 1) ia3:0 data 7 data 6 data 5 data 4 data 3 data 2 data 1 data 0 0001 rss1 rss0 res res rig3 rig2 rig1 rig0 rig3:0 right input gain select. the least significant bit of this 16-level gain select represents +1.5 db. maximum gain is +22.5 db. res reserved for future expansion. write zeros (lo) to all reserved bits. rss1:0 right input source select. these bits select the input source for the right gain stage preceding the right adc. 0 right line 1 source selected 1 right auxiliary 1 source selected 2 right line 2 source selected 3 right line 1 post-mixed output loopback source selected this registers initial state after reset is: 0000 0000 (00h). left auxiliary #1 input control register (index address 2) ia3:0 data 7 data 6 data 5 data 4 data 3 data 2 data 1 data 0 0010 lmx1 res res lx1g4 lx1g3 lx1g2 lx1g1 lx1g0 lx1g4:0 left auxiliary input #1 gain select. the least significant bit of this 32-level gain/attenuate select represents C1.5 db. lx1g4:0 = 0 produces a +12 db gain. lx1g4:0 = 01000 (8 decimal) produces 0 db gain. maximum attenuation is C34.5 db. gains referred to 2.0 v p-p full-scale output level. res reserved for future expansion. write zeros (lo) to all reserved bits. lmx1 left auxiliary #1 mute. this bit, when set hi, will mute the left channel of the auxiliary #1 input source. this bit is set hi after reset. this registers initial state after reset is: 1000 0000 (80h). right auxiliary #1 input control register (index address 3) ia3:0 data 7 data 6 data 5 data 4 data 3 data 2 data 1 data 0 0011 rmx1 res res rx1g4 rx1g3 rx1g2 rx1g1 rx1g0 rx1g4:0 right auxiliary input #1 gain select. the least significant bit of this 32-level gain/attenuate select represents C1.5 db. rx1g4:0 = 0 produces a +12 db gain. rx1g4:0 = 01000 (8 decimal) produces 0 db gain. maximum attenuation is C34.5 db. gains referred to 2.0 v p-p full-scale output level. res reserved for future expansion. write zeros (lo) to all reserved bits. rmx1 right auxiliary #1 mute. this bit, when set to hi, will mute the right channel of the auxiliary #1 input source. this bit is set to hi after reset. this registers initial state after reset is: 1000 0000 (80h).
AD1847 rev. b C14C left auxiliary #2 input control register (index address 4) ia3:0 data 7 data 6 data 5 data 4 data 3 data 2 data 1 data 0 0100 lmx2 res res lx2g4 lx2g3 lx2g2 lx2g1 lx2g0 lx2g4:0 left auxiliary #2 gain select. the least significant bit of this 32-level gain/attenuate select represents C1.5 db. lx2g4:0 = 0 produces a +12 db gain. lx2g4:0 = 01000 (8 decimal) produces 0 db gain. maximum attenuation is C34.5 db. gains referred to 2.0 v p-p full-scale output level. res reserved for future expansion. write zeros (lo) to all reserved bits. lmx2 left auxiliary #2 mute. this bit, when set hi, will mute the left channel of the auxiliary #2 input source. this bit is hi after reset. this registers initial state after reset is: 1000 0000 (80h). right auxiliary #2 input control register (index address 5) ia3:0 data 7 data 6 data 5 data 4 data 3 data 2 data 1 data 0 0101 rmx2 res res rx2g4 rx2g3 rx2g2 rx2g1 rx2g0 rx2g4:0 right auxiliary #2 gain select. the least significant bit of this 32-level gain/attenuate select represents C1.5 db. rx2g4:0 = 0 produces a +12 db gain. rx2g4:0 = 01000 (8 decimal) produces 0 db gain. maximum attenuation is C34.5 db. gains referred to 2.0 v p-p full-scale output level. res reserved for future expansion. write zeros (lo) to all reserved bits. rmx2 right auxiliary #2 mute. this bit, when set hi, will mute the right channel of the auxiliary #2 input source. this bit is hi after reset. this registers initial state after reset is: 1000 0000 (80h). left dac control register (index address 6) ia3:0 data 7 data 6 data 5 data 4 data 3 data 2 data 1 data 0 0110 ldm res lda5 lda4 lda3 lda2 lda1 lda0 lda5:0 left dac attenuate select. the least significant bit of this 64-level attenuate select represents C1.5 db. lda5:0 = 0 pro- duces a 0 db attenuation. maximum attenuation is C94.5 db. res reserved for future expansion. write zeros (lo) to all reserved bits. ldm left dac mute. this bit, when set hi, will mute the left channel output. auxiliary inputs are muted independently with the left auxiliary input control registers. this bit is hi after reset. this registers initial state after reset is: 1000 0000 (80h). right dac control register (index address 7) ia3:0 data 7 data 6 data 5 data 4 data 3 data 2 data 1 data 0 0111 rdm res rda5 rda4 rda3 rda2 rda1 rda0 rda5:0 right dac attenuate select. the least significant bit of this 64-level attenuate select represents C1.5 db. rda5:0 = 0 produces a 0 db attenuation. maximum attenuation must be at least C94.5 db. res reserved for future expansion. write zeros (lo) to all reserved bits. rdm right dac mute. this bit, when set hi, will mute the right dac output. auxiliary inputs are muted independently with the right auxiliary input control registers. this bit is hi after reset. this registers initial state after reset is: 1000 0000 (80h).
AD1847 rev. b C15C data format register (index address 8) ia3:0 data 7 data 6 data 5 data 4 data 3 data 2 data 1 data 0 1000 res fmt c/l s/m cfs2 cfs1 cfs0 csl the contents of this register can not be changed except when the AD1847 is in the mode change enable (mce) state (i.e., the mce bit in the control word is hi). write attempts to this register when the AD1847 is not in the mce state will not be successful. csl clock source select. this bit selects the clock source to be used for the audio sample rate. 0 xtal1 (24.576 mhz) 1 xtal2 (16.9344 mhz) cfs2:0 clock frequency divide select. these bits select the audio sample rate frequency. the audio sample rate depends on which clock source is selected and the frequency of the clock source. divide xtal1 xtal2 cfs2:0 factor 24.576 mhz 16.9344 mhz 0 3072 8.0 khz 5.5125 khz 1 1536 16.0 khz 11.025 khz 2 896 27.42857 khz 18.9 khz 3 768 32.0 khz 22.05 khz 4 448 not supported 37.8 khz 5 384 not supported 44.1 khz 6 512 48.0 khz 33.075 khz 7 2560 9.6 khz 6.615 khz note that the AD1847s internal oscillators can be overdriven by external clock sources at the crystal inputs. this is the configuration used by serial bus slave codecs in daisy-chained multiple codec systems. if an external clock source is ap- plied, it will be divided down by the selected divide factor. the external clock need not be at the recommended crystal frequencies. s/m stereo/mono select. this bit determines how the audio data streams are formatted. selecting stereo will result with alter- nating samples representing left and right audio channels. mono playback plays the same audio sample on both channels. mono capture only captures data from the left audio channel. 0 mono 1 stereo c/l companded/linear select. this bit selects between a linear digital representation of the audio signal or a nonlinear, com- panded format for all input and output data. the type of linear pcm or the type of companded format is defined by the fmt bits. 0 linear pcm 1 companded fmt format select. this bit defines the format for all digital audio input and output based on the state of the c/l bit. linear pcm (c/l = 0) companded (c/l = 1) 0 8-bit unsigned linear pcm 8-bit m -law companded 1 16-bit signed linear pcm 8-bit a-law companded res reserved for future expansion. write zeros (lo) to all reserved bits. this registers initial state after reset is: 0000 0000 (00h).
AD1847 rev. b C16C interface configuration register (index address 9) ia3:0 data 7 data 6 data 5 data 4 data 3 data 2 data 1 data 0 1001 res res res res acal res res pen pen playback enable. this bit will enable the playback of data in the format selected. pen may be set and reset without setting the mce bit. 0 playback disabled 1 playback enabled acal autocalibrate enable. this bit determines whether the AD1847 performs an autocalibrate when exiting from the mode change enable (mce) state. if the acal bit is not set, the previous autocalibration values are used when returning from the mode change enable (mce) state and no autocalibration takes place. autocalibration must be preformed after initial power-up for proper operation. this bit is hi after reset. 0 no autocalibration 1 autocalibration allowed note: the acal bit can only be changed when the AD1847 is in the mode change enable (mce) state. res reserved for future expansion. write zeros (lo) to all reserved bits. this registers initial state after reset is: 0000 1000 (08h). pin control register (index address 10) ia3:0 data 7 data 6 data 5 data 4 data 3 data 2 data 1 data 0 1010 xctl1 xctl0 clkts res res res res res clkts clock three-state. if the bm bit is hi, and the clkts bit is hi, then the clkout pin will be three-stated. if the bm bit is hi, and the bit clkts is lo, then the clkout pin is not three-stated. if the bm bit is lo, then the clkout pin is always three-stated. xctl1:0 external control. the state of these independent bits is reflected on the respective xctl1 and xctl0 pins of the AD1847. 0 ttl logic lo on xctl1, xctl0 pins 1 ttl logic hi on xctl1, xctl0 pins res reserved for future expansion. write zeros (lo) to all reserved bits. this registers initial state after reset is: 0000 0000 (00h). invalid address (index address 11) ia3:0 data 7 data 6 data 5 data 4 data 3 data 2 data 1 data 0 1011 inval inval inval inval inval inval inval inval inval writes to this index address are ignored. index readback of this index address will return the status word.
AD1847 rev. b C17C miscellaneous information register (index address 12) ia3:0 data 7 data 6 data 5 data 4 data 3 data 2 data 1 data 0 1100 frs tssel res res res res res res the miscellaneous information register can only be changed when the AD1847 is in the mode change enable (mce) state. changes to this register are updated at the next serial data frame sync (sdfs) boundary. if frs is lo (i.e., 32 slots per frame), and either tssel or frs change in the first sample of a frame, the change is not updated at the second sample of the same frame, but at the first sample of the next frame. tssel transmit slot select. this bit determines which tdm time slots the AD1847 should transmit on. 0 transmit on time slots 3, 4 and 5. used when sdi and sdo are tied together (i.e., 1-wire system). 1 transmit on slots 0, 1 and 2. used when sdi and sdo are independent inputs and outputs (i.e., 2-wire system). frs frame size. this bit selects the number of time slots per frame. 0 selects 32 slots per frame (two samples per frame sync or frame sync at half the sample rate). 1 selects 16 slots per frame (one sample per frame sync or frame sync at the sample rate). res reserved for future expansion. write zeros (lo) to all reserved bits. this registers initial state after reset is: 0000 0000 (00h). digital mix control register (index address 13) ia3:0 data 7 data 6 data 5 data 4 data 3 data 2 data 1 data 0 1101 dma5 dma4 dma3 dma2 dma1 dma0 res dme dme digital mix enable. this bit enables the digital mix of the adcs output with the dacs input. when enabled, the data from the adcs is digitally mixed with other data being delivered to the dacs (regardless of whether or not playback [pen] is enabled, i.e., set). if there is a capture overrun, then the last sample captured before overrun will be used for the digital mix. if playback is enabled (pen set) and there is a playback underrun, then a midscale zero will be added to the digital mix data. 0 digital mix disabled (muted) 1 digital mix enabled dma5:0 digital mix attenuation. these bits determine the attenuation of the adc output data mixed with the dac input data. the least significant bit of this 64-level attenuate select represents C1.5 db. maximum attenuation is C94.5 db. res reserved for future expansion. write zeros (lo) to all reserved bits. this registers initial state after reset is: 0000 0000 (00h). invalid address (index address 14) ia3:0 data 7 data 6 data 5 data 4 data 3 data 2 data 1 data 0 1110 inval inval inval inval inval inval inval inval inval writes to this index address are ignored. index readback of this index address will return the status word. invalid address (index address 15) ia3:0 data 7 data 6 data 5 data 4 data 3 data 2 data 1 data 0 1111 inval inval inval inval inval inval inval inval inval writes to this index address are ignored. index readback of this index address will return the status word.
AD1847 rev. b C18C serial data interface the AD1847 serial data interface uses a time division multi- plex (tdm) scheme that is compatible with dsp serial ports configured in multi-channel mode with either 32 or 16 16-bit time slots. an AD1847 is always the serial bus master, transmit- ting the serial clock (sclk) and the serial data frame sync (sdfs). the AD1847 always receives control and playback data in time slots 0, 1 and 2. the AD1847 will transmit status or index register readback and capture data in time slots 0, 1 and 2 if tssel = 1, and will transmit status or index register readback and capture data in time slots 3, 4 and 5 if tssel = 0. the following table in figure 7 shows an example of how the time slots might be assigned. in this example design, which uses the adsp-21xx dsp, each frame is divided into 32 time slots of 16-bits each (frs = 0). two audio samples are contained in the 32 time slots, with a single frame sync (sdfs) at the beginning of the frame. the adsp-21xx serial port (sport0) supports 32 time slots. the format of the first 16 time slots (sample n) is the same as the format of the second 16 time slots (sample n+1). in this ex- ample, 24 time slots are used, as indicated below. note that time slots 12 through 15 and 28 through 31 are unused in this example, and that figure 7 presumes that tssel = 0 (1-wire system). slot number source destination format 0, 16 AD1847 control word 1, 17 asic AD1847 left playback data 2, 18 right playback data 3, 19 AD1847 status word/ index readback 4, 20 AD1847 asic left capture data 5, 21 right capture data 0, 16 AD1847 control word 1, 17 dsp AD1847 left playback data 2, 18 right playback data 3, 19 AD1847 status word/ index readback 4, 20 AD1847 dsp left capture data 5, 21 right capture data 6, 22 dsp control 7, 23 asic dsp left processed playback data 8, 24 right processed playback data 9, 25 dsp status 10, 26 dsp asic left processed capture data 11, 27 right processed capture data figure 7. time slot assignment example note that in this 1-wire system example, the digital signal processor (dsp) and isa bus interface asic (asic) use the same slots to communicate to the AD1847. this reduces the number of total time slots required and eliminates the need for the AD1847 to distinguish between dsp data and asic data. also, in this example the asic and the dsp do not send data to the AD1847 at the same time, so separate slots are unnecessary. the digital data in the serial interface is pipelined up to 2 samples deep. this pipelining is required to properly resolve the interface between the relatively fast fixed sclk rate, and the relatively slow sample rates (and therefore frame sync rates) at which the AD1847 is capable of running. at low sample rates, two samples of data can be serviced in a fraction of a sample pe- riod. for example, at an 8 khz sample rate, 32 time slots only consume 32 16 (1/12.288 mhz) = 41.67 m s out of a 125 m s period. the two-deep data pipeline thus allows sample overrun (capture) and sample underrun (playback) to be avoided. figure 8 represents a logical view of the slot utilization between devices. AD1847 sdi sdo 0, 1, 2, 16, 17, 18 asic adsp-21xx dr dt dt dr note: dsp must have two serial ports 6, 7, 8, 22, 23, 24 9, 10, 11, 25, 26, 27 3, 4, 5, 19, 20, 21 0, 1, 2, 16, 17, 18 3, 4, 5, 19, 20, 21 figure 8. time slot allocation example note that this is a system specific 1-wire example. for non-dsp operation, the dsp is either not present or disabled. if the dsp is present, the asic configures the dsp through slot 6 (and slot 22) to three-state its outputs in time slots 0, 1 and 2 (and slots 16, 17 and 18). the asic can then enable its drivers for time slots 0, 1 and 2 (and slots 16, 17 and 18). for dsp operation, the asic three-states its outputs for time slots 0, 1 and 2 (and slots 16, 17 and 18) and enables the dsp drivers for slots 0, 1 and 2 (and slots 16, 17, and 18). an application note is available from analog devices with addi- tional information on interfacing to the AD1847 serial port. this application note can be obtained through your local ana- log devices representative, or downloaded from the dsp bulle- tin board service at (617) 461-4258 (8 data bits, no parity, 1 stop bit, 300/1200/2400/4600 baud).
AD1847 rev. b C19C control word data 15 data 14 data 13 data 12 data 11 data 10 data 9 data 8 clor mce rreq res ia3 ia2 ia1 ia0 data 7 data 6 data 5 data 4 data 3 data 2 data 1 data 0 data7 data6 data5 data4 data3 data2 data1 data0 left playback data data 15 data 14 data 13 data 12 data 11 data 10 data 9 data 8 data15 data14 data13 data12 data11 data10 data9 data8 data 7 data 6 data 5 data 4 data 3 data 2 data 1 data 0 data7 data6 data5 data4 data3 data2 data1 data0 right playback data data 15 data 14 data 13 data 12 data 11 data 10 data 9 data 8 data15 data14 data13 data12 data11 data10 data9 data8 data 7 data 6 data 5 data 4 data 3 data 2 data 1 data 0 data7 data6 data5 data4 data3 data2 data1 data0 status word data 15 data 14 data 13 data 12 data 11 data 10 data 9 data 8 res res rreq res id3 id2 id1 id0 data 7 data 6 data 5 data 4 data 3 data 2 data 1 data 0 res res orr1 orr0 orl1 orl0 aci init index readback data 15 data 14 data 13 data 12 data 11 data 10 data 9 data 8 clor mce rreq res ia3 ia2 ia1 ia0 data 7 data 6 data 5 data 4 data 3 data 2 data 1 data 0 data7 data6 data5 data4 data3 data2 data1 data0 left capture data data 15 data 14 data 13 data 12 data 11 data 10 data 9 data 8 data15 data14 data13 data12 data11 data10 data9 data8 data 7 data 6 data 5 data 4 data 3 data 2 data 1 data 0 data7 data6 data5 data4 data3 data2 data 1 data0 right capture data data 15 data 14 data 13 data 12 data 11 data 10 data 9 data 8 data15 data14 data13 data12 data11 data10 data9 data8 data 7 data 6 data 5 data 4 data 3 data 2 data 1 data 0 data7 data6 data5 data4 data3 data2 data1 data0
AD1847 rev. b C20C ia3:0 data 7 data 6 data 5 data 4 data 3 data 2 data 1 data 0 index 0000 lss1 lss0 res res lig3 lig2 lig1 lig0 0 0001 rss1 rss0 res res rig3 rig2 rig1 rig0 1 0010 lmx1 res res lx1g4 lx1g3 lx1g2 lx1g1 lx1g0 2 0011 rmx1 res res rx1g4 rx1g3 rx1g2 rx1g1 rx1g0 3 0100 lmx2 res res lx2g4 lx2g3 lx2g2 lx2g1 lx2g0 4 0101 rmx2 res res rx2g4 rx2g3 rx2g2 rx2g1 rx2g0 5 0110 ldm res lda5 lda4 lda3 lda2 lda1 lda0 6 0111 rdm res rda5 rda4 rda3 rda2 rda1 rda0 7 1000 res fmt c/l s/m cfs2 cfs1 cfs0 csl 8 1001 res res res res acal res res pen 9 1010 xctl1 xctl0 clkts res res res res res 10 1011 inval inval inval inval inval inval inval inval 11 1100 frs tssel res res res res res res 12 1101 dma5 dma4 dma3 dma2 dma1 dma0 res dme 13 1110 inval inval inval inval inval inval inval inval 14 1111 inval inval inval inval inval inval inval inval 15 figure 9. register map summary control register mapping summary a detailed map of the control register bit assignments is summa- rized for reference in figure 9. daisy-chained multiple codecs multiple AD1847s can be configured in a daisy-chain system with a single master codec and one or more slave codecs. codecs in a daisy-chained configuration are synchronized at the sample level. the master and slave AD1847s should be powered-up together. if this is not possible, the slave(s) should power-up before the master codec, such that the slave(s) are ready when the master starts to drive the serial interface, and a serial data frame sync (sdfs) can synchronize the master and slave(s). the sample rate for the master and slave(s) should be pro- grammed together. if this is not possible, the slave(s) should be programmed before the master AD1847. a slave AD1847 enters a time-out period after a new sample rate has been selected. during this time-out period, a slave will ignore any activity on the sdfs signal (i.e., frame syncs). there is no software means to determine when a slave has exited from this time-out period and is ready to respond to frame syncs. however, as long as the AD1847 master is driving the serial interface, a frame sync will not occur before the slave codec(s) are ready. note that the time slots for all slave AD1847s must be assigned to those slots which immediately follow the time slots consumed by the master AD1847 so that the tso (time slot output)/tsi (time slot input) signaling operates properly. for example, in a 2-wire system with one master and one slave, the time slot as- signment should be 0, 1, 2 (16, 17, 18) for the master AD1847, and 3, 4, 5 (19, 20, 21) for the slave AD1847. figure 10 illustrates the connection between master and slave(s) in a daisy-chained, multiple codec system. note that the tsi pin of the master codec should be tied to digital ground. the xtal1i pin of the slaves should be connected to digital ground, and xtal1o pin should be left unconnected, while the xtal2i pin should be connected to the clkout pin of the AD1847 master, and the xtal2o pin generates a driven version of the clkout signal applied to the xtal2i pin. initialization and procedures reset and power down a total reset of the AD1847 is defined as any event which requires both the digital and analog section of the AD1847 to return to a known and stable state. total reset mode, as well as power down, occurs when the pwrdown pin of the AD1847 has been asserted low for minimum power consumption. when the pwrdown signal is deasserted, the AD1847 must be cali- brated by setting the acal bit and exiting from the mode change enable (mce) state. the reset occurs, and only resets the digital section of the AD1847, when the reset pin of the AD1847 has been as- serted lo to initialize all registers to known values. see the reg- ister definitions for the exact values initialized. the register reset defaults include tssel = 0 (1-wire system) and frs = 0 (32 slots per frame). if the target application requires a 2-wire system design or 16 slots per frame, the AD1847 can be bootstrapped into these configurations.
AD1847 rev. b C21C 2 xtal1i,o xtal2i,o tso clkout AD1847 (master) 2 sclk sdfs sdi sdo 16.9344 mhz 24.576 mhz tsi tsi xtal2i tso xtal1i (slave 1) sclk sdfs sdi sdo xtal1o xtal2o n/c tsi xtal2i tso xtal1i (slave 2) sclk sdfs sdi sdo xtal1o xtal2o n/c figure 10a. one-wire daisy-chained codec interconnect 2 xtal1i, o xtal2i, o tso clkout AD1847 (master) 2 sclk sdfs sdi sdo 16.9344 mhz 24.576 mhz tsi tsi xtal2i tso xtal1i (slave 1) sclk sdfs sdi sdo xtal1o xtal2o n/c tsi xtal2i tso xtal1i (slave 2) sclk sdfs sdi sdo xtal1o xtal2o n/c figure 10b. two-wire daisy-chained codec interconnect to bootstrap into tssel = 1 (i.e., 2-wire system design), the host cpu or dsp must transmit to the AD1847 in slot 0 a control word with the mce bit set hi, ia3:0 = 1100 to address the miscellaneous information index register, and data7:0 = x100 000 to set the tssel bit hi. to bootstrap into frs = 1 (i.e., 16 slots per frame), the host cpu or dsp must transmit to the AD1847 in slot 0 a control word with the mce bit set hi, ia3:0 = 1100 to address the miscellaneous information index register, and data7:0 = 1x00 0000 to set the frs bit hi. the host cpu or dsp must maintain the mce bit set hi in slot 16, which is the control word of the second sample of the frame, so that the AD1847 does not initiate autocalibration prematurely. at the next frame sync, the AD1847 will be reconfigured. the AD1847 must be reset after power up. when the reset signal is deasserted, the AD1847 will autocalibrate when the mce bit is reset lo (i.e., when exiting the mode change en- able state) only if the acal bit is set. if the acal bit is not set, the previous autocalibration values will be used. the AD1847 will not function properly unless an auto- calibration is performed after power up. during power down, the serial port digital output pins and the analog output pins take the following states: sclkClo if bm is hi (i.e., bus master), input pin if bm is lo (i.e., bus slave) sdfsClo if bm is hi, input pin if bm is lo sdoCthree-state tsoCthree-state clkoutClo if bm hi, three-state if bm is lo v ref Cpulled to analog ground l_out, r_ outC pulled to analog ground clock connections and clock rates when the AD1847 is configured as a bus slave (bm = lo), the xtal1i pin should be connected to digital ground, and the xtal2i pin should be tied to the clkout of the AD1847 bus master. the xtal1o and the xtal2o pins should be left unconnected. when the AD1847 is configured as a bus master (bm = hi), the xtal1i and the xtal1o pin should be con- nected to a 24.576 mhz crystal, and the xtal2i and xtal2o pin should be connected to a 16.9344 mhz crystal. when xtal1 is selected (by resetting the csl bit lo in the data format register) as the clock source, the sclk pin will generated a serial clock at 12.288 mhz (or one half of the crys- tal frequency applied at xtal1), and the clkout pin will also generate a clock output at 12.288 mhz when the AD1847 is in bus master mode (bm = hi). when xtal2 is selected (by setting the csl bit hi in the data format register) as the clock source, the sclk pin will generate a serial clock at 11.2896 mhz (or two thirds of the crystal frequency applied at xtal2), and the clkout pin will generate a clock output at 16.9344 mhz when the AD1847 is in bus master mode (bm = hi). the clkout pin will be three-stated when the AD1847 is placed in bus slave mode (bm = lo). when the selected frame size is 32 slots per frame (by resetting the frs bit lo in the miscellaneous information register), the sdfs pin will generate a serial data frame sync at the frequency of the selected sample rate divided by two, when the AD1847 is in bus master mode (bm = hi). when the selected frame size is 16 slots per frame (by setting the frs bit hi in the miscella- neous information register), the sdfs pin will generate a serial data frame sync at the frequency of the selected sample rate, when the AD1847 is in bus master mode (bm = hi).
AD1847 rev. b C22C when the AD1847 is in bus slave mode (bm = lo), the tsi pin should be connected to the tso pin of the AD1847 master or slave which has been assigned to the preceding time slots. the signal on the tso pin is essentially the signal received on the tsi pin, but delayed by 3 or 6 time slots from tsi (depend- ing on the state of tssel). the frequency of the transitions on the tsi and tso lines is equivalent to the frequency on the sdfs pin. when the AD1847 is in bus master mode (bm = hi), the tsi pin should be connected to digital ground. the signal on the tso pin is essentially the same as the signal output on the sdfs pin, but delayed by 3 or 6 time slots from sdfs (again, depending on the state of tssel). mode change enable state the AD1847 must be in the mode change enable (mce) state before any changes to the acal bit of the interface configura- tion register, the data format register, or the miscellaneous information register are allowed. note that the mce bit does not have to be reset lo in order for changes to take effect. digital mix digital mix is enabled via the dme bit in the digital mix con- trol register. the digital mix routes the digital data from the adcs to the dacs. the mix can be digitally attenuated via bits also in the digital mix control register. the adc data is summed with the dac data supplied at the digital bus inter- face. when digital mix is enabled and the pen bit is not set, adc data is summed with zeros to produce the dac output. if the sum of the digital mix (adc output and dac input from the serial bus interface) is greater than full scale, the AD1847 will send a positive or negative full scale value to the dacs, whichever is appropriate (clipping). autocalibration the AD1847 has the ability to calibrate its adcs and dacs for greater accuracy by minimizing dc offsets. autocalibration oc- curs whenever the AD1847 exits from the mode change enable (mce) state and the acal bit in the interface configuration register has been set. the completion of the autocalibration sequence can be deter- mined by polling the autocalibration in-progress (aci) bit in the status word. this bit will be hi while the autocalibration is in progress and lo once autocalibration has completed. the autocalibration sequence will take at least 384 sample periods. the autocalibration procedure is as follows: 1. mute both left and right aux1 and aux2 inputs via the left auxiliary input and right auxiliary input control registers. 2. place the AD1847 in the mode change enable (mce) state using the mce bit of the AD1847 control word. set the acal bit in the interface configuration register. 3. exit from the mode change enable state by resetting the mce bit. 4. poll the aci bit in the AD1847 status word for a hi (autocalibration in progress), then poll the aci bit for a lo (autocalibration complete). 5. unmute the aux inputs, if used. if acal is not set, the AD1847 is muted for 128 sample peri- ods after resetting the mce bit, and the aci bit in the status word is set hi during this 128 sample periods. autocalibration must be performed after power-up to ensure proper operation of the AD1847. exiting from the mce state always causes aci to go hi. if the acal bit is set when mce state is exited, then the aci bit will be hi for 384 sample periods. if the acal bit is reset when mce is exited, then the aci bit will be hi for 128 sample periods. changing sample rates the internal states of the AD1847 are synchronized by the selected sample frequency defined in the data format register. the changing of either the clock source or the clock frequency divide requires a special sequence for proper AD1847 operation. 1. mute the outputs of the AD1847 and enter the mode change enable (mce) state by setting the mce bit of the AD1847 control word. 2. during a single atomic or nondivisible write cycle, change the clock frequency divide select (cfs) and/or the clock source select (csl) bits of the data format register to the desired values. cfs and csl can be programmed in the same control word as mce. 3. the init bit in the status word will be set hi at the last sample of the next frame to indicate that the serial port will be disabled for a timeout period. 4. the AD1847 requires a period of time to resynchronize its internal states to the newly selected clock. during this time, the AD1847 will be unable to respond at its serial interface port (i.e., no frame syncs will be generated). the time-out period is 2 21 3 sclk ? 170 ms after power-up, and ? 5 ms for subsequent changes of sample rate. 5. exit the mode change enable state by resetting the mce bit. upon exiting the mce state, an autocalibration of duration 384 sample periods or an output mute of duration 128 sample periods occurs, depending on the state of the acal bit. 6. poll the aci bit in the AD1847 status word for a hi (indi- cating that autocalibration is in progress) then poll the aci bit for a lo (indicating that autocalibration has completed). once the aci bit has been read back lo, normal operation of the codec can resume. the csl and cfs bits cannot be changed unless the AD1847 is in the mode change enable state (i.e., the mce bit in the AD1847 control word is set). attempts to change the contents of the data format register without mce set will result in the write cycle not being recognized (the bits will not be updated). the mce bit should not be reset until after the init bit in the AD1847 status word is detected hi. after the init bit is de- tected hi, the serial port is disabled. when the next frame sync arrives (after the time-out period), all internal clocks are stable and the serial port is ready for normal operation.
AD1847 rev. b C23C data format definitions there are four data formats supported by the AD1847: 16-bit sign ed, 8-bit unsigned, 8-bit companded m -law, and 8-bit com- panded a-law. the AD1847 supports these four formats because each of them have found wide use in important applications. 16-bit signed format the 16-bit signed format (also called 16-bit twos-complement) is the standard method of representing 16-bit digital audio. this format yields 96 db of dynamic range and is common in con- sumer compact disk audio players. this format uses the value C 32768 (8000h) to represent minimum analog amplitude while 32767 (7fffh) represents maximum analog amplitude. inter- mediate values are a linear interpolation between minimum and maximum amplitude values. max min 8000h digital value analog value 0000h 7fffh figure 11. 16-bit signed format 8-bit unsigned format the 8-bit unsigned format is commonly used in the personal computer industry. this format delivers 48 db of dynamic range. the value 0 (00h) is used to represent minimum analog amplitude while 255 (ffh) is used to represent maximum ana- log amplitude. intermediate values are a linear interpolation be- tween minimum and maximum amplitude values. the least significant byte of the 16-bit internal data is truncated to create the 8-bit output samples. max min 00h digital value analog value 7fh ffh figure 12. 8-bit unsigned format 8-bit companded formats the 8-bit companded formats ( m -law and a-law) are used in the telecommunications industry. both of these formats are used in isdn communications and workstations; m -law is the standard for the united states and japan while a-law is used in europe. companded audio allows either 64 db or 72 db of dynamic range using only 8-bits per sample. this is accomplished using a nonlinear formula which assigns more digital codes to lower am- plitude analog signals at the expense of resolution of higher am- plitude signals. the m -law format of the AD1847 conforms to the bell system m = 255 companding law while the a-law format conforms to ccitt a law models. figure 13 shows approxi- mately how both the m -law and a-law companding schemes be- have. refer to the standards mentioned above for an exact definition. max min 00h ffh 80h aah ?law a-law d5h 2ah digital value analog value figure 13. 8-bit companded format applications circuits the AD1847 stereo codec has been designed to require a mini- mum of external circuitry. the recommended circuits are shown in figures 14 through 22. analog devices estimates that the to- tal cost of all the components shown in these figures, including crystals, to be less than $3 in 10,000 quantities. industry-standard compact disc line-levels are 2 v rms centered around analog ground. (for other audio equipment, line level is much more loosely defined.) the AD1847 soundport is a +5 v only powered device. line level voltage swings for the AD1847 are defined to be 1 v rms for a sine wave adc input and 0.707 v rms for a sine wave dac output. thus, 2 v rms input ana- log signals must be attenuated and either centered around the reference voltage intermediate between 0 v and +5 v or ac-coupled. the v ref pin will be at this intermediate voltage, nominally 2.25 v. it has limited drive but can be used as a volt- age datum to an op amp input. note, however, that dc-coupled inputs are not recommended, as they provide no performance benefits with the AD1847 architecture. furthermore, dc offset differences between multiple dc-coupled inputs create the po- tential for clicks when changing the input mux selection.
AD1847 rev. b C24C circuits for 2 v rms line-level inputs and auxiliaries are shown in figure 14 and figure 15. note that these are divide-by-two resistive dividers. the input resistor and 560 pf (1000 pf) capacitor provide the single-pole of antialias filtering required for the adcs. if line-level inputs are already at the 1 v rms levels expected by the AD1847, the resistors in parallel with the 560 pf (1000 pf) capacitors can be omitted. if the application does not route the aux2 inputs to the adcs, then no antialias filtering is required (only the 1 m f ac coupling capacitor). 5.1k 560pf npo 5.1k 0.33 m f r_line1 r_line2 5.1k 560pf npo 5.1k 0.33 m f l_line1 l_line2 figure 14. 2 v rms line-level input circuit for line inputs 3.3k 1000pf npo 4.3k l_aux1 l_aux2 1 m f r_aux1 r_aux2 3.3k 1000pf npo 4.3k 1 m f figure 15. 2 v rms line-level input circuit for aux inputs figure 16 illustrates one example of how an electret condenser microphone requiring phantom power could be connected to the AD1847. v ref is shown buffered by an op amp; a transistor like a 2n4124 will also work well for this purpose. note that if a battery-powered microphone is used, the buffer and r2s are not needed. the values of r1, r2, and c should be chosen in light of the mic characteristics and intended gain. typical values for these might be r1 = 20 k w , r2 = 2 k w , and c = 220 pf. 1/2 ssm2135 or ad820 r2 r2 left electret condenser microphone input 5k 0.33 m f l_line1 l_line2 1 m f r1 c 1/2 ssm2135 or ad820 v ref 5k 0.33 m f r_line1 r_line2 1 m f r1 c 1/2 ssm2135 or ad820 v ref right electret condenser microphone input figure 16. phantom-powered microphone input circuit figure 17 shows ac-coupled line outputs. the resistors are used to center the output signals around analog ground. if dc-coupling is desired, v ref could be used with op amps as mentioned previously. 47k 1 m f l_out 47k 1 m f r_out figure 17. line output connections a circuit for headphone drive is illustrated in figure 18. drive is supplied by +5 v operational amps. the circuit shown ac couples the headphones to the line output. ssm2135 20k 470 m f 18k v ref headphone left 20k 470 m f 18k headphone right l_out r_out figure 18. headphone drive connections figure 19 illustrates reference bypassing. v refi should only be connected to its bypass capacitors. 10 m f 0.1 m f v refi 10 m f v ref figure 19. voltage reference bypassing figure 20 illustrates signal-path filtering capacitors, l_filt and r_filt. the AD1847 must use 1.0 m f capacitors. the 1.0 m f capacitors required by the AD1847 can be of any type. 1.0 m f lfilt 1.0 m f rfilt figure 20. external filter capacitor connections
AD1847 rev. b C25C the crystals shown in the crystal connection circuitry of figure 21 should be fundamental-mode and parallel-tuned. two sources for the exact crystals specified are component market- ing services in massachusetts, u.s. at 617/762-4339 and cardinal components in new jersey, u.s. at 201/746-0333. note that using the exact data sheet frequencies is not required and that external clock sources can be used to overdrive the ad18 47s internal oscillators. (see the description of the cfs2:0 control bits above.) if using an external clock source, apply it to the crystal input pins while leaving the crystal output pins un- connected. attention should be paid to providing low-jitter ex- ternal input clocks . xtal1i xtal1o 20 64pf 20 64pf 24.576mhz xtal2i xtal2o 20 64pf 20 64pf 16.9344mhz figure 21. crystal connections analog devices also recommends a pull-down resistor on the pwrdown signal. good, standard engineering practices should be applied for power-supply decoupling. decoupling capacitors should be placed as close as possible to package pins. if a separate analog power supply is not available, the circuit shown in figure 22 is recommended when using a single +5 v supply. ferrite beads suffice for the inductors shown. this circuitry should be as close to the supply pins as is practical. +5v supply 0.1 m f ferrite 1 m f 0.1 m f v dd v dd v dd 0.1 m f v dd 0.1 m f ferrite 1 m f 1.6 0.1 m f 1 m f v cc v cc 0.1 m f 0.1 m f figure 22. recommended power supply bypassing analog devices recommends a split ground plane as shown in figure 23. the analog plane and the digital plane are connected directly under the AD1847. splitting the ground plane directly under the soundport codec is optimal because analog pins will be located directly above the analog ground plane and digital pins will be located directly above the digital ground plane for the best isolation. the digital and analog grounds should be tied together in the vicinity of the AD1847. other schemes may also yield satisfactory results. if the split ground plane recommended here is not possible, the AD1847 should be entirely over the analog ground plane with the asic and dsp over the digital plane. digital ground plane analog ground plane pwrdown v cc bm l_aux2 AD1847 figure 23. recommended ground plane
AD1847 rev. b C26C frequency response plots 10 ?20 1.0 ?0 ?10 0.1 ?00 0.0 ?0 ?0 ?0 ?0 ?0 ?0 0 ?0 ?0 0.8 0.9 0.7 0.6 0.5 0.4 0.3 0.2 db sample frequency ?f s figure 24. AD1847 analog-to-digital frequency response (full-scale line-level inputs, 0 db gain) db sample frequency ?f s 10 ?20 0.70 ?0 ?10 ?00 0.40 ?0 ?0 ?0 ?0 ?0 ?0 0 ?0 ?0 0.64 0.68 0.60 0.56 0.52 0.48 0.44 figure 25. AD1847 analog-to-digital frequency response Ctransition band (full-scale line-level inputs, 0 db gain) 10 ?20 ?0 ?10 ?00 ?0 ?0 ?0 ?0 ?0 ?0 0 ?0 ?0 1.0 0.1 0.0 0.8 0.9 0.7 0.6 0.5 0.4 0.3 0.2 db sample frequency ?f s figure 26. AD1847 digital-to-analog frequency response (full-scale inputs, 0 db attenuation) db sample frequency ?f s 10 ?20 ?0 ?10 ?00 ?0 ?0 ?0 ?0 ?0 ?0 0 ?0 ?0 0.70 0.40 0.64 0.68 0.60 0.56 0.52 0.48 0.44 figure 27. AD1847 digital-to-analog frequency response Ctransition band (full-scale inputs, 0 db attenuation)
AD1847 rev. b C27C t hz t dv t pd1 t s t h sclk sdfs sdi sdo bit 15 bit 14 bit 0 bit 15 bit 14 bit 0 figure 28. time slot timing diagram sclk sdfs sdi or sdo tso 15 321 0151413 t pd1 last valid time slot t pd2 14 13 figure 29. tso timing diagram t rpwl reset pwrdown figure 30. reset and power down timing diagram 16-bit stereo 8-bit stereo sclk sdfs 16-bit mono 8-bit mono control left pb sdi/ sdo time slot 0 time slot 1 time slot 2 control status right playback right playback left playback left capture control status left capture left playback left capture sdi/ sdo sdi/ sdo 0 left cap status right pb right cap 0 control left pb sdi/ sdo 0 left cap status left cap 0 figure 31. serial data format, 2-wire system (tssel = 1) 16-bit stereo 8-bit stereo sclk sdfs time slot 0 time slot 1 time slot 2 time slot 3 time slot 4 time slot 5 16-bit mono 8-bit mono control left right status left right control left status left playback capture control left status left control left right status left right 0 0 0 left 0 left sdi/ sdo sdi/ sdo sdi/ sdo sdi/ sdo figure 32. serial data format, 1-wire system (tssel = 0)
AD1847 rev. b C28C outline dimensions dimensions shown in inches and (mm). 44-lead plcc (p-44a) 0.032 (0.81) 0.026 (0.66) 0.021 (0.53) 0.013 (0.33) 0.056 (1.42) 0.042 (1.07) 0.025 (0.63) 0.015 (0.38) 0.180 (4.57) 0.165 (4.19) 0.63 (16.00) 0.59 (14.99) 0.110 (2.79) 0.085 (2.16) 0.040 (1.01) 0.025 (0.64) 0.050 (1.27) bsc 0.656 (16.66) 0.650 (16.51) sq 0.695 (17.65) 0.685 (17.40) sq 0.048 (1.21) 0.042 (1.07) 0.048 (1.21) 0.042 (1.07) 40 6 top view 39 29 18 17 pin 1 identifier 7 28 0.020 (0.50) r 44-terminal plastic thin quad flatpack (tqfp) (st-44) top view (pins down) 1 33 34 44 11 12 23 22 0.018 (0.45) 0.012 (0.30) 0.031 (0.80) bsc 0.394 (10.0) sq 0.472 (12.00) sq 0.057 (1.45) 0.053 (1.35) 0.006 (0.15) 0.002 (0.05) seating plane 0.063 (1.60) max 0.030 (0.75) 0.018 (0.45) c1871bC2C8/96 printed in u.s.a. index page product overview . . . . . . . . . . . . . . . . . . . . . . . . 1 AD1847 specifications . . . . . . . . . . . . . . . . . . . . . 2 ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 audio functional description . . . . . . . . . . . 7 analog inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 analog mixing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 analog-to-digital datapath . . . . . . . . . . . . . . . . . . . . . 7 digital-to-analog datapath . . . . . . . . . . . . . . . . . . . . . 7 digital mixing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 analog outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 digital data types . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 power supplies and voltage reference . . . . . . . . . . . . . 8 clocks and sample rates . . . . . . . . . . . . . . . . . . . . . . . 8 control registers . . . . . . . . . . . . . . . . . . . . . . . . 9 control register mapping . . . . . . . . . . . . . . . . . . . . . . 9 control word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 left/right playback/capture data . . . . . . . . . . . . . . . 10 status word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . : 11 index readback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 indirect mapped registers . . . . . . . . . . . . . . . . . . . . . 12 left input control register . . . . . . . . . . . . . . . . . . . . 13 right input control register . . . . . . . . . . . . . . . . . . . 13 left auxiliary #1 input control register . . . . . . . . . . 13 right auxiliary #1 input control register . . . . . . . . . 13 left auxiliary #2 input control register . . . . . . . . . . 14 right auxiliary #2 input control register . . . . . . . . . 14 left dac control register . . . . . . . . . . . . . . . . . . . . . 14 right dac control register . . . . . . . . . . . . . . . . . . . . 14 data format register . . . . . . . . . . . . . . . . . . . . . . . . . 15 interface configuration register . . . . . . . . . . . . . . . . . 16 pin control register . . . . . . . . . . . . . . . . . . . . . . . . . . 16 invalid address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 miscellaneous information register . . . . . . . . . . . . . . 17 digital mix control register . . . . . . . . . . . . . . . . . . . 17 invalid address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 serial data interface . . . . . . . . . . . . . . . . . . . . . . . . . . 18 control register mapping summary . . . . . . . . . . . . . 20 daisy-chained multiple codecs . . . . . . . . . . . . . . . . . 20 initialization and procedures . . . . . . . . . . 21 reset and power down . . . . . . . . . . . . . . . . . . . . . . . 21 clock connections and clock rates . . . . . . . . . . . . . . 21 mode change enable state . . . . . . . . . . . . . . . . . . . . 22 digital mix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 autocalibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 changing sample rates . . . . . . . . . . . . . . . . . . . . . . . 22 data format definitions . . . . . . . . . . . . . . . . 23 16-bit signed format . . . . . . . . . . . . . . . . . . . . . . . . . 23 8-bit unsigned format . . . . . . . . . . . . . . . . . . . . . . . . 23 8-bit companded formats . . . . . . . . . . . . . . . . . . . . . 23 applications circuits . . . . . . . . . . . . . . . . . . . . 23 frequency response plots . . . . . . . . . . . . . . . 26 timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . 27 outline dimensions . . . . . . . . . . . . . . . . . . . . . . 28 all brand or product names mentioned are trademarks or regis- tered trademarks of their respective holders.

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